Embedded Systems · ARM · Real-Time
E-WarP
Envelope-aWare Predictive Model
Embedded platforms pack CPUs and accelerators onto one memory bus, and shared bandwidth turns predictable code into missed deadlines. E-WarP profiles memory demand offline, predicts execution time under a bandwidth budget, and enforces it by coordinating MemGuard software bandwidth regulation for the CPU cores with ARM QoS hardware for the accelerator — before the system ever ships.
Why shared memory causes unpredictable execution
Modern embedded platforms pack general-purpose CPUs alongside specialized accelerators onto a single chip, and both share the same DRAM. A CPU core issues a steady trickle of memory requests, while an accelerator like APEX issues requests in large, bursty waves — and when both compete for the same DRAM controller, execution time stops being a property of the code alone. Existing approaches such as MemGuard could already regulate CPU traffic, but none provided coordinated control over hardware accelerator traffic — leaving accelerators unmanaged, or reacting only after a deadline had already slipped.
- Only CPU memory traffic is regulated
- Accelerator bursts remain unmanaged
- Contention is detected only after it degrades timing
- Deadlines are found unsafe only at runtime
- CPU and accelerator traffic are profiled together
- A predictive model estimates slowdown before deployment
- MemGuard regulates CPU traffic; ARM QoS hardware, driven by the same predicted allocation, enforces the accelerator's budget
- Deadlines are verified safe before the system ships
Offline profiling predicts execution time before deployment
E-WarP profiles application execution offline and tracks how memory demand accumulates over time — a cumulative envelope, not just an instantaneous rate. That envelope makes it possible to predict execution time under any candidate bandwidth budget before the system ever runs on target hardware. The prediction is only half the story: E-WarP integrates MemGuard, an existing software-based bandwidth regulator for CPU traffic, with ARM QoS hardware mechanisms for accelerator traffic, so the same offline model translates directly into a coordinated allocation across both.
Instead of measuring instantaneous bandwidth, E-WarP tracks the cumulative memory envelope: total transactions accumulated at each point in time, a running count that only ever increases.
The E-WarP Pipeline
Everything up to runtime configuration happens offline — only enforcement runs on the real-time critical path.
Application binary running on the target board
Raw memory-transaction trace
Capture how memory demand actually varies during execution
<1% (dedicated profiling core)
System Architecture
Offline profiling reveals true memory demand
A bare-metal profiler runs in its own partition on a dedicated core, reading ARM PMU hardware counters directly — no instrumentation, no shared memory with the application it measures.
Sampling every 1.5 microseconds through a dedicated DDR controller, it builds a dense, per-core and per-accelerator picture of memory behavior at less than 1% overhead.
E-WarP runs a bare-metal profiler in a dedicated partition on CPU3. The partitioning hypervisor ensures no shared state, no synchronization, and no coupling between profiling and application execution.
Software-managed, hardware-enforced isolation
E-WarP does not implement its own bandwidth regulator. It integrates two existing, complementary partitioning mechanisms: MemGuard, a software-based DRAM bandwidth regulation framework, continues to manage CPU-core traffic exactly as it does elsewhere; ARM QoS, a hardware mechanism built into the platform, regulates memory traffic from the APEX accelerator.
MemGuard alone could already regulate CPU traffic, but gave no coordinated control over accelerator traffic. E-WarP's contribution is extending bandwidth management to the accelerator by driving ARM QoS hardware from the same predicted allocation MemGuard uses — so the two mechanisms enforce one coordinated budget instead of operating independently.
Implementation details
MemGuard and ARM QoS are integrated within the Jailhouse partitioning hypervisor, the same hypervisor used to isolate the profiler from the application — providing a single, unified runtime environment on the NXP S32V234 rather than two independent systems.
MemGuard regulates CPU-core traffic directly; ARM QoS hardware, driven by the same predicted allocation, meters the APEX accelerator. MemGuard alone has no coordinated control over accelerator traffic — E-WarP's contribution is driving both mechanisms from one prediction, not replacing either.
Built on Real Hardware
E-WarP was profiled, predicted, and enforced entirely on the NXP S32V234 automotive platform — the same class of hardware used in real ADAS deployments.
- ARM Cortex-A53 clusterGeneral-purpose CPU cores running application and OS code
- APEX acceleratorVision-processing accelerator issuing bursty memory traffic
- Dual DDR controllersOne dedicated to the profiler, one to the workload — no shared path
- MemGuardExisting software framework that regulates CPU-core memory traffic — integrated by E-WarP, not built from scratch
- ARM QoS hardwareHardware mechanism that meters and enforces the APEX accelerator's bandwidth quota, driven by E-WarP's predicted allocation
- Jailhouse partitionsIsolate the profiler from the application, and provide the unified runtime environment where MemGuard and ARM QoS are integrated
Results: Accurate Predictions, Coordinated Enforcement
E-WarP was evaluated on the NXP S32V234 automotive platform to test prediction accuracy, joint software/hardware bandwidth management, and predictable execution under contention.
Prediction Accuracy
6% average overprediction across evaluated workloads.
Predicted execution time tracked measured runtime closely across CPU-only and accelerator-assisted workloads, at every tested bandwidth budget.
That trace is converted into the same cumulative envelope used everywhere else in E-WarP — one model, reused end to end.
Joint CPU and Accelerator Bandwidth Management
MemGuard and ARM QoS hardware jointly manage bandwidth across heterogeneous compute.
MemGuard held each CPU core to its assigned bandwidth share, while ARM QoS hardware — driven by E-WarP's predicted allocation — enforced the APEX accelerator's quota directly under contention. Neither mechanism alone covered both traffic sources; coordinated by E-WarP, together they did.
Predictable Execution Under Contention
Execution stayed within predicted bounds even under simultaneous CPU and accelerator contention.
Under concurrent CPU and APEX workloads, measured execution time remained inside the predicted envelope at every tested bandwidth budget — the same guarantee schedulability analysis depends on.
Real Automotive Hardware Evaluation
All measurements were collected on physical NXP S32V234 silicon.
Profiling, prediction, and enforcement were evaluated end to end on the same automotive-grade hardware used in real ADAS deployments — not simulation.
My Role
Profiling Infrastructure
Designed and implemented a low-overhead runtime profiler using ARM PMU hardware counters to capture fine-grained memory behavior with less than 1% execution overhead.
Prediction Methodology
Developed the cumulative memory-envelope methodology that predicts application slowdown under different DRAM bandwidth budgets with approximately 6% average overprediction.
ARM QoS Integration
Integrated ARM QoS hardware mechanisms alongside MemGuard's software-based CPU regulation, driving both from one predicted allocation to enforce accelerator-side bandwidth limits for the APEX accelerator.
Experimental Evaluation
Designed experiments on the NXP S32V234 automotive platform, validated prediction accuracy, and demonstrated predictable execution under shared-memory contention.
Embedded Systems Implementation
Integrated the profiling, prediction, and enforcement mechanisms within the Jailhouse partitioning hypervisor for a single, coordinated execution environment.
This project required work across embedded systems, operating systems, computer architecture, performance analysis, and real-time scheduling. I designed and implemented the profiling infrastructure and prediction methodology, integrated MemGuard software bandwidth regulation with ARM QoS hardware enforcement, and ran the experimental evaluation — all coordinated within the Jailhouse hypervisor on the NXP S32V234 platform.
E-WarP demonstrates how offline profiling, predictive performance modeling, and coordinated software/hardware bandwidth management can deliver predictable execution for heterogeneous embedded platforms before deployment.